1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly a semiconductor memory device having sub dummy bit lines and sub dummy word lines.
2. Description of the Related Art
A dynamic random access memory (DRAM) includes a plurality of bit lines and word lines perpendicularly intersecting each other. A plurality of unit cells each including one transfer transistor and one data storage capacitor are formed at every intersection of the bit lines and word lines. As DRAM density increases, the area available of the chip for the unit cell and peripheral circuitry is reduced.
Referring to FIG. 1, a common layout for a semiconductor memory device includes a plurality of main memory cell arrays 200. Each memory cell array 200 is divided into a plurality of sub memory cell arrays 300 that each include multiple unit cells 105. A column decoder 103 and a row decoder 101 are arranged respectively at the left and bottom sides of the main memory cell array 200. A peripheral circuit region 100 is used for peripheral circuitry that controls operation of the unit cells 105.
Referring to FIG. 2, a layout of the sub memory cell array 300 and peripheral circuitry includes a sense amplifier region 400, a strap region (not shown), and a sub word line driver region 500 interposed between the adjacent sub memory cell arrays 300. The strap region is a metal wire region formed over the unit cell 105 and a gate polysilicon layer that compensates for time delays in a connected word line. In the sub word line driver region 500, a plurality of driver elements drive the sub word lines.
The strap region and the sub word line driver region 500 raise several manufacturing problems. The sub memory cell array 300 has a higher topology than the adjacent strap region and the adjacent sub word line driver region 500. The different topologies make it difficult to carry out precise layout processes. A diffused reflection of an optical beam during the photolithographic process make it difficult to produce a desired layout for the unit cells 105 on the borders of the sub memory cell arrays 300.
In order to solve such problems, the borders of the sub memory cell array 300 includes sub dummy word lines DWL and sub dummy bit lines DBL that perpendicularly intersect each other. Dummy cells are located at every intersection of the sub dummy word lines DWL and the sub dummy bit lines DBL. The sub dummy word line DWL is usually biased to a ground voltage VSS and the sub dummy bit line DBL is usually biased to a bitline precharge level VCC/2.
Due to process defects, a data storage capacitor connected to the sub dummy bit line DBL may unintentionally be electrically coupled to a data storage capacitor connected to a sub normal bit line NBL. This process defect between nodes causes an undesirable short bridge 121, as shown in FIG. 4. The short bridge 121 causes failures when carrying out performance tests such as burn-in testing.
FIG. 3 is a detailed circuit diagram of the sub memory cell array 300 including the sub dummy word lines DWL and the sub dummy bit lines DBL. The sub dummy bit line DBL is interposed between the sub word line driver region 500 and the sub memory cell array 300. The sub dummy bit line DBL is coupled to transfer transistors 108 by way of direct contact (DC) 107. The transfer transistors 108 and the data storage capacitors 119 constitute dummy unit cells 115a, 115b, 117a and 117b. A normal unit cell 113 has the same structure as the dummy unit cells 115a, 115b, 117a and 117b.
FIG. 4 is a detail circuit diagram of the sub memory cell array 300 showing the dummy unit cell 115b operatively connected to a normal unit cell 116a via the short bridge 121. The transfer transistor 108 of the dummy unit cell 115a has a drain connected to the sub dummy bit line DBL by way of the contact 107, a gate connected to a word line WL0, and a source connected to the data storage capacitor 119 by way of a buried contact. Similarly, the transfer transistor 108 in the dummy unit cell 115b has a drain connected to the sub dummy bit line DBL, a gate connected to a word line WL1, and a source connected to the data storage capacitor 119.
The transfer transistor 108 of the normal unit cell 116a has a drain connected to the normal bit line NBLB, a gate connected to the word line WL2, and a source connected to the data storage capacitor 109. The transfer transistor 108 of the normal unit cell 116b has a drain connected to the normal bit line NBLB, a gate connected to the word line WL3, and a source connected to the data storage capacitor 109.
Process defects can cause the storage capacitor 119 of the dummy unit cell 115b to connect to the storage capacitor 109 of the normal unit cell 116a via the short bridge 121.
When a row address strobe RAS is driven from the logic high level to the logic low level, the dynamic RAM receives an external row address. The row address is processed and transferred to the row decoder 101 shown in FIG. 1, activating a selected one of the word lines WL0-WLn. A few upper bits of the address transferred to the row decoder 101 are used as control signals for controlling the sense amplifier 400 of FIG. 3. The short bridge 121 is not a desired element that exits in the sub memory cell array 300. If a word line WLi (where i=0-n) is activated, data stored in the data storage capacitor 109 is loaded onto the normal bit line NBLB via the transfer transistor 108. The data on the bit line pair BL/BLB is amplified by the sense amplifier 400 and transferred to an input/output line I/O. The data is then transferred to off-chip data processing circuitry.
In the case where the sub memory cell array 300 includes the short bridge 121, the sense amplifier 400 cannot sense (i.e., read out) the data accurately. Namely, the data storage capacitor 109 of the normal unit cell 116a shares the data (i.e., the charge) with the storage capacitor 119 of the dummy unit cell 115b. When the word line WL1 is activated, the data stored into the storage capacitor 109 of the normal unit cell 116a is transferred to the dummy bit line DBL via the transfer transistor 108 of the dummy unit cell 115b. As a result, the data stored in the storage capacitor 109 of the normal unit cell 116a will have an invalid voltage level of VCC/2. If the word line WL2 is activated shortly thereafter, data with the invalid voltage level will be loaded on the normal bit line NBLB. The sense amplifier 400 cannot accurately sense the invalid data.